1. Field of the Invention
The present invention relates to an analog-to-digital converter, and more specifically to a successive approximation type analog-to-digital converter which includes a plurality of local digital-to-analog converters of a given resolution and which can provide a resolution higher than the given resolution of the digital-to-analog converter.
2. Description of Related Art
At present, digital technique has been widely used in various fields. As a result, analog-to-digital converters (called "A/D converter" hereinafter) and a digital-to-analog converter (called "D/A converter" hereinafter) become very important as an interface between an analog signal and a digital signal.
Among different types of A/D converters, a successive approximation type A/D converter is known as one which can operate at an intermediate or high speed and can provide a digital signal composed of a relatively large number of bits.
Referring to FIG. 1, there is shown a block diagram of a typical example of a conventional successive approximation type A/D converter. The shown A/D converter includes an analog signal input terminal 10 connected to a first input of a sample and hold circuit 12, which has a second input connected to an output of a local D/A converter 14. The sample and hold circuit 12 has a pair of outputs corresponding to the pair of inputs, these outputs being connected to a pair of inputs of a comparator 16, whose output is connected to a successive approximation register 18. This register 18 has parallel outputs connected to the local D/A converter 14. Further, a serial output of the register 18 is connected to a digital signal output terminal 20.
With this arrangement, the local D/A converter is so set to generate a voltage V.sub.FS /2 corresponding to a half of the full scale voltage V.sub.FS when it receives the parallel output of the register 18 composed of the most significant bit (MSB) of "1" and the other bits of "0". In this condition, the voltage of the analog signal held in the sample and hold circuit 12 is compared with the output voltage V.sub.FS /2 of the local D/A converter by the comparator 16. The result of comparison is outputted to the successive approximation register 18, which changes its content, i.e., a digital data to be supplied to the local D/A converter 14. For example, when the input analog signal is larger than V.sub.FS /2, the MSB of the register 18 is maintained at "1" as it is, and the second significant bit (2SB) is changed to "1" from "0". The other bits are maintained at "0". Accordingly, the output voltage of the D/A converter 14 is brought into 3 V.sub.FS /4. On the other hand, when the input analog signal is smaller than V.sub.FS /2, the MSB and 2SB of the register 18 are changed to "0" and "1", respectively, and the other bits are maintained at "0". In this case, the D/A converter 14 generates V.sub.FS /4. Thus, the value of the MSB is determined, and then, the next comparison is made between the input analog signal and the reference voltage V.sub.FS /4 or 3 V.sub.FS /4 of the local D/A converter 14, so that the 2SB will be determined. Thus, similar operation will be repeated to successively determine each bit of the digital data until the least significant bit (LSB) is determined.
In the above mentioned successive approximation A/D converter, the local D/A converter is generally divided into two types, one of which includes a resistor string or ladder and the other of which includes a capacitor array.
At present, D/A converters, which have a resolution of 8 bits to 10 bits and which can be used as the local D/A converter 14 in the above mentioned conventional successive approximation A/D converter, can be manufactured in mass production manner with high reliability and stability in accordance with recent advanced integrated circuit technique. Therefore, A/D converters having a relatively small bit number can be manufactured with reliability.
However, components fabricated on an integrated circuit have a certain limit in uniformity of characteristics, and therefore, it is the present status that it is difficult to obtain a D/A converter having a higher resolution. For example, in order to obtain a D/A converter having a resolution of 12 bits to 16 bits, it is necessary to constitute a circuit with discrete parts such as resistors and capacitors of the accuracy matching with the required resolution. Otherwise, it is necessary to use a fine adjustment means such as a Laser trimming. In this case, however, the cost for forming required elements becomes very large, and also, elements having a sufficient reliability cannot be obtained.
As mentioned above, in the case that a D/A converter of a large bit number is constituted in combination with a single resistor string or ladder or a single capacitor array, a sufficient accuracy cannot be obtained because the D/A converter cannot maintain a monotonic increase over the full range because of dispersion of element characteristics. For overcoming this problem, there has been proposed to use a plurality of D/A converters in parallel. For example, if two D/A converters are combined in parallel, the combined D/A converter can have a full scale corresponding to the sum of respective full scales of the two unitary D/A converters. Assuming that first and second unitary D/A converters have full scales FS1 and FS2, respectively, the combined D/A converter has a full scale FS equal to (FS1+FS2).
In the combined D/A converter, the first unitary D/A converter will increment its output in response to increment of a digital input. When the MSB of the digital input changes from "0" to "1", the logic value "1" is supplied to all input bits of the first unitary D/A converter so that it outputs its full scale FS1. Thereafter, the second unitary D/A converter will increment in response to increment of the digital input, so that the output of the second D/A converter is added to the output of the first D/A converter to provide a combined output.
Further, an interpolation type which uses a master D/A converter and a slave D/A converter has been proposed. In this case, one step of the master D/A converter is divided further finely by the slave D/A converter.
However, the first mentioned accumulation method using a plurality of unitary D/A converters in parallel is disadvantageous in that a gain error of each unitary D/A converter is accumulated, with the result that the overall D/A converter has a large error in total linearity. On the other hand, the interpolation type has such a defect that it cannot have a monotonic increase if a slave D/A converter has an increased step error.